1. Field of the Invention
The present invention relates to a high-voltage detecting circuit for detecting a high voltage applied to an input terminal for a use of, for example, a mode setting and the like.
2. Description of the Related Art
Japanese Patent Kokai No.5-259880, for example, can be cited as a prior art reference.
Conventionally, a voltage higher than a power supply voltage is applied to an input terminal which is commonly used for applying address signals and the like, for setting an integrated circuit to a test mode in a semiconductor device. The applied voltage is detected by a high-voltage detecting circuit to switch the integrated circuit into the test mode.
A conventional high-voltage detecting circuit comprises, for example, a P-channel MOS transistor (hereinafter, referred to as xe2x80x9cPMOSxe2x80x9d) which has a source connected to an input terminal, a drain connected to a ground voltage GND through a resistor or the like, and a gate applied with a power supply voltage VCC. The voltage level at the drain of the PMOS is output as a detected high voltage signal.
When the common input terminal is applied with an intermediate voltage between the power supply voltage VCC and ground voltage GND (an address signal and the like) in the high-voltage detecting circuit as mentioned above, a threshold voltage Vth of the PMOS impedes a current from flowing into the PMOS, causing the level xe2x80x9cLxe2x80x9d to appear at the drain. On the other hand, when the input terminal is applied with a predetermined voltage (voltage higher than VCC+Vth), the PMOS turns on so that the level at the drain goes to xe2x80x9cH.xe2x80x9d It is therefore possible to rely on the level at the drain of the PMOS to detect whether or not a high voltage is applied.
The conventional high-voltage detecting circuit, however, has the following problems.
The miniaturization of integrated circuits drives gate oxide films to be made thinner, but this trend of reducing the thickness results in a lower breakdown of the gate oxide film, so that it becomes difficult to apply a high voltage to the gate.
On the other hand, some tests conducted on semiconductor devices include a high-voltage application test which involves applying the power supply voltage VCC set higher than the voltage that should be applied during a normal operation. In this event, the high voltage applied to the input terminal for setting a semiconductor device to a test mode is increased further beyond the predetermined high voltage (VCC+Vth). Generally, the input terminal applied with the high voltage is commonly used as an input terminal for address signals and the like for avoiding an increase in the number of terminals of the semiconductor device.
Thus, if the input terminal is applied with a voltage higher than the predetermined voltage for setting the test mode, the high voltage will destroy a gate oxide film of an input circuit for the address signal.
To solve the aforementioned problem, the present invention provides a high-voltage detecting circuit for detecting application of a high voltage for a mode setting, and holding and outputting a high-voltage detecting signal. The high-voltage detecting circuit includes an input terminal which is commonly applied with a high voltage and an input signal, said high voltage being higher than a power supply voltage and said input signal having a voltage equal to or lower than the power supply voltage; a reset unit for outputting an initial reset signal when the power supply is turned on; a transistor having a source connected to said input terminal and a gate applied with the power supply voltage, said transistor turning on in response to the application of said high voltage to said input terminal, and turning off in response to the application of the input signal to said input terminal; and a latch which is reset by the initial reset signal, and set when said transistor is turned on to output a high-voltage detecting signal.
According to the present invention, the following operation is performed, since the high-voltage detecting circuit is configured in the foregoing manner.
As the power supply voltage is applied, the reset unit outputs the initial reset signal to reset the latch. As the input terminal is applied with a signal equal to or lower than the power supply voltage in this state, the input signal is processed as an input signal for a logic operation.
Then, as the input terminal is applied with a high voltage higher than the power supply voltage, the transistor turns on to set the latch which responsively outputs a high-voltage detecting signal. This causes, for example, a transition to a test mode, followed by a test operation.